Currently, products called CPU (Central Processing Unit) and MPU (Micro-Processing Unit) are put to practical use as processor units that can easily perform various data processing tasks. In a data processing system utilizing such a processor unit, various application programs, in which a plurality of instruction codes are written, and various processing data are stored in a memory device. The processor unit sequentially reads out the instruction codes and the processing data from the memory device and performs a plurality of operations one after another. Therefore it is possible to perform various data processing tasks using one processor unit.
In data processing using such a processor unit, a plurality of operations are sequentially performed one after another. Therefore, it is difficult to perform complex data processing at high speed since the processor unit has to read out instruction codes from the memory device for each processing task.
Meanwhile, when only one type of data processing needs to be performed, a logic circuit can be realized with hardware so that it performs that particular data processing and it is not necessary for the processor unit to sequentially read out a plurality of instruction codes from the memory device and sequentially perform a plurality of operations one after another. As a result, it is possible to perform complex data processing at high speed, however, only one type of data processing can be performed.
In other words, in a data processing system where application programs can be switched, various data processing tasks can be performed, but it is difficult to perform them at high speed since the configuration of the hardware is fixed. On the other hand, it is possible to realize high speed data processing with a hardware logic circuit, but only one type of data processing can be performed since the application program cannot be changed.
In order to meet the demands of both data processing speed and program changeability, array-type processors as data processing devices in which the configuration of the hardware changes according to the software are disclosed in Patent Documents 1 and 2.
In the array-type processor of Patent Document 1 shown in FIG. 13, numerous small-scale processor elements 105, along with numerous programmable switch elements 106, are disposed in matrix in a data path section 102, and a state transition controller 101 is disposed alongside of the data path section 102. The state transition controller 101 has a state transition table memory, where a state number of a next cycle is stored, and the number is sequentially read out according to the current internal state of the state transition controller 101 and/or the conditions of an external event 209. The state number read out is converted into an instruction specifying signal (address signal) of the data path section and supplied to the data path section 102 via an operation control path 103. The plurality of the processor elements 105 individually perform data processing corresponding to instruction codes individually set in data and have the plurality of the switch elements 106 individually disposed alongside of switch-control the relationship of the electrical connection to each other.
In the array-type processor configured as described, the state transition controller 101 sequentially switches the context of the data path section 102, which is constituted by the instruction codes for the plurality of the processor elements and the plurality of the switch elements, according to a computer program at every operation cycle. Therefore, the array-type processor is capable of continuously performing parallel computing, according to the computer program.
Further, an array-type processor that can efficiently operate even in the case where a plurality of state transitions are simultaneously performed by having a plurality of state transition controllers operate in conjunction with each other is disclosed in Patent Document 2. The operation of the processor elements in this array-type processor is substantially the same as above.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-312481A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2004-133781A